PLL2002A Serial Input PLL Frequency Synthesizer

The PLL2002A is a serial data programmable PLL Frequency Syntheseizer. Ratios of reference frequency divider and input frequency divider can be independently set.

Pin	Name	Description
1	RI	Reference X-tal Oscillator Input
2	RO	Reference X-tal Oscillator Output
3	NC	No Connection
4	Vcc	Positive Supply Voltage - 5 Volt
5	PD	Phase Detector Output - VCO Voltage Out
6	GND	Ground
7	LD	Loop Detector - Loop Detected=HIGH - Not Detected=LOW
8	Fin	VCO Frequency In
9	CL	Clock from CPU
10	Data	Data from CPU
11	EN	Enable from CPU
12	DOA	Charge pump output for activ lowpass filter
13	NC	No Connection
14	Test	Connect to Vcc
15	O_V	Phase detector output to differential lowpass filter
16	O_R	Phase detector output to differential lowpass filter

Serial Data for PLL2002A

Serial data input timing

Divider data setting procedure

Input data must be MSB first. Final bit (17th bit) is assigned to the control bit.
Data are written into shift register at the rising edge of the CLK signal.
When LE is HIGH, data is transferred from the shift register to either the latch of reference divider or input divider. Thus data must be written on the shift register while LE is remaining L0W.

While all bits of the N latch to are "0", the N counter will be disabled, DOA, DOP are floating, and the supply current will be decreased.
While all bits of the R latch are "0", oscillator will be disabled.
While all bits of R and N latches are "0" , supply current decreases to 10uA or less.

This counter shows the number of hits since the 29th January 2000

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